Field
Integrated circuit processing.
Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip and/or to send and/or receive signals external to the device(s). Common types of interconnections include copper and copper alloy interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias. It is not uncommon for integrated circuit to have multiple levels of interconnections (e.g., five or six levels) separated by dielectric materials. In prior integrated circuit structures, a popular dielectric material for use as an interlayer dielectric (ILD) was silicon dioxide (SiO2). Currently, efforts are focused on minimizing the effective dielectric constant of an ILD so materials having a dielectric constant lower than SiO2 (low k dielectric material) have garnered significant consideration. Many of these materials, such as carbon, silicon, oxygen based materials are porous.
Developing and implementing low k ILD based integrated circuits may utilize complementary and compatible photolithography and etching processes to pattern devices that will not attack underlying layers critical to device performance. Representatively, contacts made out of tungsten are used, for example, as vertical interconnects between the source/drain junction of transistor devices and the first level interconnect, which typically consists of a dual damascene metal and a via used to connect to the contact layer in multilevel interconnect schemes. Current post patterning cleaning schemes as applied to a first dual damascene metal layer (M1/V0) deposited on a contact have a generally narrow process window due to the requirements of being able to remove both the metal hard mask (e.g., titanium or titanium nitride), photoresist, and residual etch polymer while simultaneously not etching tungsten (in the contact exposed thru the V0), copper or the low k ILD.
One process to form a first dual damascene metal level (M1) on an integrated circuit structure uses a titanium nitride hard mask to create a dual damascene M1V0 about a tungsten plug. The titanium nitride hard mask is conductive and therefore must be removed to avoid line-to-line shorting. Wet clean chemistries have not been identified that can strip titanium nitride without also damaging the tungsten contact layer. To address this issue, one solution is that after the W1V0 patterning and prior to titanium nitride removal, a sacrificial light absorbing material (SLAM) is deposited and dry etched for use as a layer to protect the underlying tungsten during the titanium nitride wet clean. This method can be costly and tends to increase the M1V0 critical dimensions due to multiple process steps which can lead to V0 to wrong contact shorting.